Already a subscriber? 
MADCAD.com Free Trial
Sign up for a 3 day free trial to explore the MADCAD.com interface, PLUS access the
2009 International Building Code to see how it all works.
If you like to setup a quick demo, let us know at support@madcad.com
or +1 800.798.9296 and we will be happy to schedule a webinar for you.
Security check
Please login to your personal account to use this feature.
Please login to your authorized staff account to use this feature.
Are you sure you want to empty the cart?
BS EN IEC 61643-21:2026 Low voltage surge protective devices - Surge protective devices connected to telecommunications and signalling networks. Requirements and test methods, 2026
- undefined
- European foreword
- Endorsement notice
- Annex ZA (normative) Normative references to international publications with their corresponding European publications [Go to Page]
- CONTENTS
- FOREWORD
- INTRODUCTION
- 1 Scope
- 2 Normative references
- 3 Terms and definitions [Go to Page]
- 3.1 Terms and definitions
- 4 Classification [Go to Page]
- 4.1 General
- 4.5 Type of SPD
- 4.8 Mounting method
- 4.13 End-of-life mode of the SPDA
- 4.14 Short-circuit protection function for OCM end-of-life mode
- 4.100 SPD configurations
- Figures [Go to Page]
- Figure 100 – SPD configurations
- 4.101 SPD Variants
- 4.102 Overstressed fault mode according to 3.1.115 [Go to Page]
- 4.102.1 Mode 1
- 4.102.2 Mode 2
- 4.102.3 Mode 3
- 4.103 Additional information about transmission and special applications
- 5 Void
- 6 Marking and other product information [Go to Page]
- 6.1 General
- 6.2 List of items
- Figure 101 – Example of U-I diagram providing three value pairs of voltage and current for impulse reset test (U1/I1, U2/I2 and U3/I3) with U1 = UC and e.g. I3 = IL
- 6.2.100 Information to be provided by the manufacturer
- 6.2.101 Information which shall be provided by the manufacturer for type testing, as applicable
- 6.3 Information about status indicator
- 7 Service conditions
- 8 Requirements [Go to Page]
- 8.1 General requirements
- 8.3 Electrical requirements [Go to Page]
- 8.3.1 Protection against electric shock
- 8.3.2 Continuous current IC
- 8.3.3 Protective conductor current IPE
- 8.3.4 Measured limiting voltage
- 8.3.5 Operating duty
- 8.3.6 Safety performance of overstressed SPDs
- 8.3.7 Insulation resistance
- 8.3.8 Dielectric withstand
- 8.3.9 Behaviour under temporary overvoltages
- 8.3.100 Impulse durability and voltage protection level
- 8.3.101 Impulse reset
- 8.3.102 AC durability, if declared by the manufacturer
- 8.3.103 Blind spot
- 8.3.104 Series resistance
- 8.3.105 Current-limiting requirements
- 8.3.106 Transmission requirements
- 8.4 Mechanical requirements [Go to Page]
- 8.4.1 General
- 8.4.5 Mechanical strength
- 8.5 Environmental and material requirements [Go to Page]
- 8.5.2 Heat resistance
- 8.5.4 Tracking resistance
- 8.5.5 Ageing behaviour under damp heat
- 8.6 Additional requirements for specific SPD designs [Go to Page]
- 8.6.1 Two port SPDs and one port SPDs with separate input/output connections
- 8.6.3 SPDs with electrically separated circuits
- 8.6.4 Total discharge current ITotal, if declared by the manufacturer
- 8.6.5 Two port SPDs
- 8.6.6 Short-circuiting SPDs
- 9 Tests [Go to Page]
- 9.1 Type testing procedures [Go to Page]
- 9.1.1 General
- Tables [Go to Page]
- Table 100 – Type test requirements
- Table 3 – Pass criteria for type tests [Go to Page]
- 9.1.2 Impulse discharge current
- 9.1.3 8/20 Current impulse
- 9.1.4 1,2/50 voltage impulse
- 9.1.5 Combination wave
- 9.1.100 Waveform tolerances of impulse categories C3 and D2
- Table 101 – Waveform tolerances combination wave
- 9.3 Electrical tests [Go to Page]
- 9.3.1 Protection against direct contact
- 9.3.2 Continuous current IC
- 9.3.3 Protective conductor current IPE
- 9.3.4 Measured limiting voltage
- 9.3.5 Operating duty test
- Table 102 – Waveform tolerances impulse categories C3 and D2 [Go to Page]
- 9.3.6 Safety performance of overstressed SPDs
- Figure 102 – Procedure for sample preparation for dedicated overstress test [Go to Page]
- 9.3.8 Dielectric withstand
- Table 7 – Dielectric impulse withstand test voltages for SPD main circuits
- Table 9 – Dielectric AC test voltages for SPD main circuits
- Table 10 – Dielectric impulse withstand test voltages for separated circuits [Go to Page]
- 9.3.9 Behaviour under temporary overvoltages (TOVs)
- 9.3.100 Impulse durability and voltage protection level
- Table 12 – Dielectric AC test voltages for separated circuits
- Figure 103 – Test circuits for impulse durability and voltage- protection level [Go to Page]
- 9.3.101 Impulse reset
- Table 103 – Categories and minimum requirements for impulse durability
- Figure 104 – Test circuits for impulse reset time [Go to Page]
- 9.3.102 AC durability
- 9.3.103 Blind spot test
- Figure 105 – Test circuits for AC durability [Go to Page]
- 9.3.104 Series resistance
- 9.3.105 Current-limiting tests
- Figure 106 – Test circuits for series resistance, current response time, current reset time, maximum interrupting voltage and operating duty test
- Table 104 – Test currents for response time
- Figure 107 – Test circuits for AC durability of the current-limiting component (e.g. X1Y1) [Go to Page]
- 9.3.106 Transmission tests
- Figure 108 – Test circuits for impulse durability of the current-limiting component (e.g. X1-Y1)
- Figure 109 – Test circuits for insertion loss
- Table 105 – Typical parameters for Figure 110
- Figure 110 – Test circuit for return loss
- Figure 111 – Test circuits for longitudinal balance
- Table 106 – Typical impedance values for longitudinal balance test
- 9.4 Mechanical tests [Go to Page]
- 9.4.3 Tests for external connections for copper conductors
- Figure 112 – Test circuit for near-end crosstalk [Go to Page]
- 9.4.4 Verification of air clearances and creepage distances
- Table 16 – Cross-sections of copper conductors for screw-type or screwless terminals
- Table 107 – Altitude correction factors for calculating the air clearances
- Table 108 – Rated impulse withstand voltages for air clearances for SPDs
- 9.5 Environmental and material tests [Go to Page]
- 9.5.2 Heat resistance
- 9.5.4 Tracking resistance
- 9.5.5 Life test under damp heat
- Table 20 – Air clearances for SPD main circuit(s)
- 9.6 Additional tests for specific SPD designs [Go to Page]
- 9.6.1 Tests for two-port SPDs and one-port SPDs with separate input/output connections
- Figure 113 – Examples for a test arrangement of the rated load current test IL [Go to Page]
- 9.6.4 Total discharge current test for multimode SPDs
- Figure 114 – Test circuits for total discharge current
- Table 109 – ITotal current distribution [Go to Page]
- 9.6.5 Tests for two port SPDs only
- Figure 115 – Examples of multimode SPDs with a common voltage-limiting component
- Annex AA (normative) Application of annexes from IEC 61643-01 [Go to Page]
- Table AA.1 – Application of annexes from IEC 61643-01
- Annex BB (informative) Example configurations for measuring UP [Go to Page]
- Figure BB.1 – Differential Mode Up measurement of Figure 100 SPDs
- Figure BB.2 – ITU-T test setup for SPD Common Mode Up measurement to C connection
- Annex CC (informative) Special resistibility in telecommunication systems
- Annex DD (informative) Bit error ratio (BER) [Go to Page]
- Table DD.1 – Test times for BER test
- Figure DD.1 – Test circuit for bit error ratio test
- Annex EE (informative) Example of transmission test methods for SPDs connected to LAN [Go to Page]
- EE.1 General
- EE.2 Abbreviated terms
- EE.3 Requirements
- Table EE.1 – List of abbreviated terms
- Table EE.2 – Typical Tests for an SPD
- EE.4 Test methods [Go to Page]
- EE.4.1 Measurement circuit
- EE.4.2 Insertion loss
- EE.4.3 NEXT, power sum NEXT
- Figure EE.1 – Measurement circuit of a channel link with up to two SPDs [Go to Page]
- EE.4.4 Return loss
- Annex FF (informative) Typical threat parameters for SPDs [Go to Page]
- Table FF.1 – SPDs parameter for typical threats
- Annex GG (informative) Examples of source voltages and currents for impulse reset test [Go to Page]
- Table GG.1 – Source voltages and currents for impulse reset test
- Annex HH (informative) Test circuit examples for testing more than one mode of protection simultaneously [Go to Page]
- HH.1 General
- HH.2 Impulse durability and voltage protection level
- HH.3 Impulse reset time
- Figure HH.1 – Test circuits for impulse durability and voltage-limiting tests
- HH.4 AC durability
- Figure HH.2 – Test circuit for impulse reset time testing two modes of protection (common mode, X1 – C and X2 – C) simultaneously of SPDs with voltage-limiting component or voltage-limiting and current-limiting component
- HH.5 AC durability for current-limiting function
- Figure HH.3 – Test circuit for AC durability testing two modes of protection (common mode, X1 – C and X2 – C) simultaneously of SPDs with voltage-limiting component or voltage-limiting and current-limiting component
- Figure HH.4 – Test circuits for AC durability of the current-limiting component
- HH.6 Impulse durability for current-limiting function
- Figure HH.5 – Test circuits for impulse durability of the current-limiting component
- Annex II (normative) Reduced test procedures [Go to Page]
- Table II.1 – Reduced test procedure for SPDs complying with IEC 61643-21:2012
- Bibliography [Go to Page]
