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IEC 62425 Ed. 2.0 en:2025 Railway applications - Communication, signalling and processing systems - Safety related electronic systems for signalling, 2025
- CONTENTS
- FOREWORD
- INTRODUCTION
- 1 Scope
- 2 Normative references
- 3 Terms, definitions and abbreviated terms [Go to Page]
- 3.1 Terms and definitions
- 3.2 Abbreviated terms
- 4 Overall framework of this document
- 5 Requirements for developing safety-related electronic systems [Go to Page]
- 5.1 General
- 5.2 The quality management process
- 5.3 The safety management process [Go to Page]
- 5.3.1 General
- 5.3.2 Guideline for structuring documentation
- 5.3.3 Safety life cycle
- 5.3.4 Safety organization
- 5.3.5 Safety plan
- 5.3.6 Hazard log
- 5.3.7 Safety requirements specification
- 5.3.8 System design for safety
- 5.3.9 Safety operation and maintenance plan
- 5.3.10 Safety verification
- 5.3.11 Safety validation
- 5.3.12 Safety qualification tests
- 5.3.13 Management of safety-related application conditions
- 5.3.14 Safety justification
- 5.3.15 Independent safety assessment
- 6 Requirements for elements following different life cycles [Go to Page]
- 6.1 General
- 6.2 Use of pre-existing items [Go to Page]
- 6.2.1 General
- 6.2.2 Requirements for use of complete pre-existing systems
- 6.2.3 Requirements for use of pre-existing equipment
- 6.3 Safety-related tools for electronic systems
- 6.4 Physical security and cybersecurity
- 7 The safety case: structure and content [Go to Page]
- 7.1 The safety case structure
- 7.2 The technical safety report
- 7.3 Generic and specific safety cases
- 7.4 Provisions for the specific application safety case
- 7.5 Dependencies between safety cases
- 8 System safety acceptance and subsequent phases [Go to Page]
- 8.1 System safety acceptance process
- 8.2 Operation, maintenance and performance monitoring
- 8.3 Modification and retrofit
- 8.4 Decommissioning and disposal
- Annexes [Go to Page]
- Annex A (normative) Safety integrity levels [Go to Page]
- A.1 General
- A.2 Safety requirements
- A.3 Safety integrity
- A.4 Determination of safety integrity requirements [Go to Page]
- A.4.1 General
- A.4.2 Risk assessment
- A.4.3 Hazard control
- A.4.4 Identification and treatment of new hazards arising from design
- A.5 Allocation of SILs [Go to Page]
- A.5.1 General aspects
- A.5.2 Relationship between SIL and associated TFFR
- Annex B (normative) Management of faults for safety-related functions [Go to Page]
- B.1 General
- B.2 General concepts [Go to Page]
- B.2.1 Detection and negation times
- B.2.2 Composition of two independent items
- B.3 Effects of faults [Go to Page]
- B.3.1 Effects of single faults
- B.3.2 Independence of items
- B.3.3 Detection of single faults
- B.3.4 Action following detection (retention of safe state)
- B.3.5 Effects of multiple faults
- B.3.6 Defence against systematic faults
- Annex C (normative) Identification of hardware component failure modes [Go to Page]
- C.1 General
- C.2 General procedure
- C.3 Procedure for integrated circuits
- C.4 Procedure for components with inherent physical properties
- C.5 General provisions concerning component failure modes
- Annex D (informative) Example of THR/TFFR/FR apportionment and SIL allocation
- Annex E (normative) Techniques and measures for the avoidance of systematic faults and the control of random and systematic faults [Go to Page]
- E.1 General
- E.2 Tables of techniques and measures
- Annex F (informative) Guidance on User Programmable Integrated Circuits [Go to Page]
- F.1 General [Go to Page]
- F.1.1 Purpose
- F.1.2 Terminology and context
- F.2 UPIC life cycle [Go to Page]
- F.2.1 General
- F.2.2 Organization, roles, responsibilities and personnel competencies
- F.2.3 UPIC Requirements
- F.2.4 UPIC Architecture and Design
- F.2.5 Logic Component Design
- F.2.6 Logic Component Coding
- F.2.7 Logic Component Verification
- F.2.8 UPIC Physical Implementation
- F.2.9 UPIC Integration
- F.2.10 UPIC Validation
- F.2.11 Requirements for use of pre-existing logic components
- F.3 Detailed technical requirements for UPIC [Go to Page]
- F.3.1 Guidance on safety architecture
- F.3.2 Protection against random faults – architectural principles
- F.3.3 Protection against systematic faults – techniques and measures
- Annex G (informative) Changes in this document compared to IEC 62425:2007
- Bibliography
- Figures [Go to Page]
- Figure 1 – Scope of the main IEC and CENELEC railway application standards
- Figure 2 – Structure of IEC 62425
- Figure 3 – Example of system life cycle
- Figure 4 – Example of design and validation portion of system life cycle
- Figure 5 – Independence of roles for different SILs and BI, phases 5 to 10
- Figure 6 – Structure of safety case
- Figure 7 – Structure of technical safety report
- Figure 8 – Examples of different usage of safety cases
- Figure 9 – Examples of different safety acceptance processes
- Figure A.1 – Safety requirements and safety integrity
- Figure A.2 – The hourglass model
- Figure A.3 – Definition of hazards with respect to the system boundary
- Figure A.4 – Example of a hazard analysis process
- Figure A.5 – Common cause failures (CCF)
- Figure A.6 – Treatment of CCF by FTA
- Figure A.7 – Relationship between SILs and techniques
- Figure B.1 – Detection and negation times
- Figure B.2 – Control of single and multiple faults
- Figure B.3 – Influences affecting the independence of items
- Figure B.4 – Detection and negation of single faults – composite fail-safety
- Figure B.5 – Detection and negation of single faults – reactive fail-safety
- Figure C.1 – Example of a 4-terminal resistor, using a hybrid thick layer technique
- Figure D.1 – Example of THR/TFFR/FR breakdown and related SIL allocation
- Figure F.1 – UPIC architecture
- Figure F.2 – UPIC development context
- Figure F.3 – Example of UPIC development life cycle
- Figure F.4 – Example of UPIC development life cycle with pre-existing components
- Figure F.5 – UPIC development techniques and measures
- Tables [Go to Page]
- Table 1 – Example of SRAC template
- Table 2 – Sections and contents of the technical safety report
- Table A.1 – The SIL table
- Table B.1 – Measures to detect faults in integrated circuits by means of periodic online testing
- Table C.1 – Resistors
- Table C.2 – Capacitors
- Table C.3 – Electromagnetic components
- Table C.4 – Diodes
- Table C.5 – Transistors
- Table C.6 – Controlled rectifiers
- Table C.7 – Surge suppressors
- Table C.8 – Opto-electronic components
- Table C.9 – Filters
- Table C.10 – Interconnection assemblies
- Table C.11 – Fuses
- Table C.12 – Switches and push/pull buttons
- Table C.13 – Lamps
- Table C.14 – Batteries
- Table C.15 – Transducers and sensors (excluding those with internal electronic circuitry)
- Table E.1 – Safety planning and quality assurance activities
- Table E.2 – Safety requirements specification
- Table E.3 – Safety organization
- Table E.4 – Architecture of system, subsystem or equipment
- Table E.5 – Design features
- Table E.6 – Failure and hazard analysis methods
- Table E.7 – Design and development of system, subsystem or equipment
- Table E.8 – Safety verification and validation of the system, subsystem or equipment
- Table E.9 – Application, operation and maintenance
- Table F.1 – Example of documentation generated during each phase
- Table F.2 – Simplified techniques and measures for protection against systematic failures
- Table F.3 – Design and verification (including all activities before synthesis)
- Table F.4 – Synthesis
- Table F.5 – Placement, routing and layout generation
- Table F.6 – Description of techniques for design
- Table F.7 – Description of techniques for synthesis
- Table F.8 – Description of techniques for placement, routing and layout generation
- Table G.1 – Clauses and subclauses – correspondence with IEC 62425:2007
- Table G.2 – Figures and tables – correspondence with IEC 62425:2007 [Go to Page]
