MADCAD.com - The Cloud-Based Reference Library

Not a subscriber? Register for a trial account.

Username:
Password:

Incorrect username/password.

Already a subscriber?

MADCAD.com Free Trial

Sign up for a 3 day free trial to explore the MADCAD.com interface, PLUS access the
2009 International Building Code to see how it all works.

If you like to setup a quick demo, let us know at support@madcad.com
or +1 800.798.9296 and we will be happy to schedule a webinar for you.

Email *
Password *
Confirm *
First Name *
Last Name *
Title
Company Name *
Company Size *
Industry *
Address *
Address 2
City *
State *	Zip *
Country *
Phone *
How did you hear about MADCAD.com? *

⨯To continue with accurate pricing,
please select your company type below:

Large goverment organizations

Large multi-national corporation (more than $5B annual revenue)

None of the above

Your company has a special pricing case for IEEE.
For pricing, please contact us by filling out the form.

Full name*
Email*
Phone
Your selection

⨯We need your input!

Are you a code official in a jurisdiction with less than 300,000 population?

Yes No

This item is only available for the code officials of jurisdictions less then 300K population.

If you do not meet the criteria item will be removed and you will be able to continue shopping other items.

⨯ We need your input!

Your company has a special pricing case for ASME.
Please make sure the information you provide below is accurate.

Company Industry
Number Of Employees
Revenue

Pricing for the ASME publications in the store is for a 1-4 employee company in Construction Industry with revenue under $500,000.
If correct company info does not match what is publicly available info we will suspend the access and contact you for correction.
Please call 1-800-798-9296 if you have any questions.
If your company has more than 5,000 employee or more than 500 mil revenue please email us at info@madcad.com to receive a special quote, use "ASME Quote" on the subject line.

Search book title

Search book content

Clear all filters Advanced Search Basic Search

Download File

eLibrary > ISO/IEC 13961:2000 Information technology -- Scalable Coherent Interface (SCI) >

ISO/IEC 13961:2000 Information technology -- Scalable Coherent Interface (SCI), 2000

Expand All

TOC Search:

ISO/IEC 13961:2000 Information technology -- Scalable Coherent Interface (SCI), 2000

CONTENTS
FOREWORD
1 Introduction [Go to Page]
1.1 Document structure
1.2 SCI overview [Go to Page]
1.2.1 Scope and directions
1.2.2 The SCI approach
1.2.3 System configurations
1.2.4 Initial physical models
1.2.5 SCI node model
1.2.6 Architectural parameters
1.2.7 A common CSR architecture
1.2.8 Structure of the specification
1.3 Interconnect topologies [Go to Page]
1.3.1 Bridged systems
1.3.2 Scalable systems
1.3.3 Interconnected systems
1.3.4 Backplane rings
1.3.5 Interconnected rings
1.3.6 Rectangular grid interconnects
1.3.7 Butterfly switches
1.3.8 Vendor-dependent switches
1.4 Transactions [Go to Page]
1.4.1 Packet formats
1.4.2 Input and output queues
1.4.3 Request and response queues
1.4.4 Switch queues
1.4.5 Subactions
1.4.6 Remote transactions (through agents)
1.4.7 Move transactions
1.4.8 Broadcast moves
1.4.9 Broadcast passing by agents
1.4.10 Transaction types
1.4.11 Message passing
1.4.12 Global clocks
1.4.13 Allocation protocols
1.4.14 Queue allocation
1.5 Cache coherence [Go to Page]
1.5.1 Interconnect constraints
1.5.2 Distributed directories
1.5.3 Standard optimizations
1.5.4 Future extensions
1.5.5 TLB purges
1.6 Reliability, availability, and support (RAS) [Go to Page]
1.6.1 RAS overview
1.6.2 Autoconfiguration
1.6.3 Control and status registers
1.6.4 Transmission-error detection and isolation
1.6.5 Error containment
1.6.6 Hardware fault retry (ringlet-local, physical layer option)
1.6.7 Software fault recovery (end-to-end)
1.6.8 System debugging
1.6.9 Alternate routing
1.6.10 Online replacement
2 References, glossary, and notation [Go to Page]
2.1 Normative references
2.2 Conformance levels
2.3 Terms and definitions
2.4 Bit and byte ordering
2.5 Numerical values
2.6 C code
3 Logical protocols and formats [Go to Page]
3.1 Packet formats [Go to Page]
3.1.1 Packet types
3.2 Send and echo packet formats [Go to Page]
3.2.1 Request-send packet format
3.2.2 Request-echo packet format
3.2.3 Response-send packet
3.2.4 Standard status codes
3.2.5 Response-echo packet format
3.2.6 Interconnect-affected fields
3.2.7 Init packets
3.2.8 Cyclic redundancy code (CRC)
3.2.9 Parallel 16-bit CRC calculations
3.2.10 CRC stomping
3.2.11 Idle symbols
3.3 Logical packet encodings [Go to Page]
3.3.1 Flag coding
3.4 Transaction types [Go to Page]
3.4.1 Transaction commands
3.4.2 Lock subcommands
3.4.3 Unaligned DMA transfers
3.4.4 Aligned block-transfer hints
3.4.5 Move transactions
3.4.6 Global time synchronization
3.5 Elastic buffers [Go to Page]
3.5.1 Elasticity models
3.5.2 Idle-symbol insertions
3.5.3 Idle-symbol deletions
3.6 Bandwidth allocation [Go to Page]
3.6.1 Fair bandwidth allocation
3.6.2 Setting ringlet priority
3.6.3 Bandwidth partitioning
3.6.4 Types of transmission protocols
3.6.5 Pass-transmission protocol
3.6.6 Low-transmission protocol
3.6.7 Idle insertions
3.6.8 High-transmission protocol
3.7 Queue allocation [Go to Page]
3.7.1 Queue reservations
3.7.2 Multiple active sends
3.7.3 Unfair reservations
3.7.4 Queue-selection protocols
3.7.5 Re-send priorities
3.8 Transaction errors [Go to Page]
3.8.1 Requester timeouts (response-expected packets)
3.8.2 Time-of-death timeout (optional, all nodes)
3.8.3 Responder-processing errors
3.9 Transmission errors [Go to Page]
3.9.1 Error isolation
3.9.2 Scrubber maintenance
3.9.3 Producer-detected errors
3.9.4 Consumer-detected errors
3.10 Address initialization [Go to Page]
3.10.1 Transaction addressing
3.10.2 Reset types
3.10.3 Unique node identifiers
3.10.4 Ringlet initialization
3.10.5 Simple-subset ringlet resets
3.10.6 Ringlet resets
3.10.7 Ringlet clears (optional)
3.10.8 Inserting initialization packets
3.10.9 Address initialization
3.11 Packet encoding [Go to Page]
3.11.1 Common encoding features (L18)
3.11.2 Parallel encoding with 18 signals (P18)
3.11.3 Serial encoding with 20-bit symbols (S20)
3.12 SCI-specific control and status registers [Go to Page]
3.12.1 SCI transaction sets
3.12.2 SCI resets
3.12.3 SCI-dependent fields within standard CSRs
3.12.4 SCI-dependent CSRs
3.12.5 SCI-dependent ROM
3.12.6 Interrupt register formats
3.12.7 Interleaved logical addressing
4 Cache-coherence protocols [Go to Page]
4.1 Introduction [Go to Page]
4.1.1 Objectives
4.1.2 SCI transaction components
4.1.3 Physical addressing
4.1.4 Coherence directory overview
4.1.5 Memory and cache tags
4.1.6 Instruction-execution model
4.1.7 Coherence document structure
4.2 Coherence update sequences [Go to Page]
4.2.1 List prepend
4.2.2 List-entry deletion
4.2.3 Update actions
4.2.4 Cache-line locks
4.2.5 Stable sharing lists
4.3 Minimal-set coherence protocols [Go to Page]
4.3.1 Sharing-list updates
4.3.2 Cache fetching
4.3.3 Cache rollouts
4.3.4 Instruction-execution model
4.4 Typical-set coherence protocols [Go to Page]
4.4.1 Sharing-list updates
4.4.2 Read-only fetch
4.4.3 Read-write fetch
4.4.4 Data modifications
4.4.5 Mid and head deletions
4.4.6 DMA reads and writes
4.4.7 Instruction-execution model
4.5 Full-set coherence protocols [Go to Page]
4.5.1 Full-set option summary
4.5.2 CLEAN-list creation
4.5.3 Sharing-list additions
4.5.4 Cache washing
4.5.5 Cache flushing
4.5.6 Cache cleansing
4.5.7 Pairwise sharing
4.5.8 Pairwise-sharing faults
4.5.9 QOLB sharing
4.5.10 Cache-access properties
4.5.11 Instruction-execution model
4.6 C-code naming conventions
4.7 Coherent read and write transactions [Go to Page]
4.7.1 Extended mread transactions
4.7.2 Cache cread and cwrite64 transactions
4.7.3 Smaller tag sizes
5 C-code structure [Go to Page]
5.1 Node structure [Go to Page]
5.1.1 Signals within a node
5.1.2 Packet transfers among node components
5.1.3 Transfer-cloud components
5.2 A node's linc component [Go to Page]
5.2.1 A linc's subcomponents
5.2.2 A linc's elastic buffer
5.2.3 Other linc components
5.3 Other node components [Go to Page]
5.3.1 A node's core component
5.3.2 A node's memory component
5.3.3 A node's exec component
5.3.4 A node's proc component
6 Physical layers [Go to Page]
6.1 Type 1 module [Go to Page]
6.1.1 Module characteristics
6.1.2 Module compatibility considerations
6.1.3 Module size
6.1.4 Warpage, bowing, and deflection
6.1.5 Cooling
6.1.6 Connector
6.1.7 Power and ground connection
6.1.8 Pin allocation for backplane parallel 18-signal encoding
6.1.9 Slot-identification signals
6.2 Type 18-DE-500 signals and power control [Go to Page]
6.2.1 SCI differential signals
6.2.2 Status lines
6.2.3 Serial Bus signals
6.2.4 Signal levels and skew
6.2.5 Power-conversion control
6.3 Type 18-DE-500 module extender cable
6.4 Type 18-DE-500 cable-link
6.5 Serial interconnection [Go to Page]
6.5.1 Serial interface Type 1-SE-1250, single-ended electrical
6.5.2 Optical interface, fiber-optic signal type 1-FO-1250
6.5.3 Test methods
Annex A (informative) Ringlet initialization
Annex B (informative) SCI design models [Go to Page]
B.1 Fast counters
B.2 Translation-lookaside-buffer coherence [Go to Page]
B.2.1 Virtual addressing
B.2.2 TLB-purge options
B.2.3 Interrupt-driven purges
B.2.4 Direct-register purges
B.2.5 Coherently purged TLBs
B.3 Coherent lock models
B.4 Coherence-performance models [Go to Page]
B.4.1 Nonblocking message queues
Bibliography
Figures [Go to Page]
Figure 1 – Physical-layer alternatives
Figure 2 – SCI node model
Figure 3 – 64-bit-fixed addressing
Figure 4 – Bridged systems
Figure 5 – Backplane rings
Figure 6 – Interconnected rings
Figure 7 – 2-D processor grids
Figure 8 – Butterfly ringlets
Figure 9 – Switch interface
Figure 10 – Subactions
Figure 11 – Send-packet format, simplified
Figure 12 – Responder queues
Figure 13 – Logical requester/responder queues
Figure 14 – Paired request and response queues
Figure 15 – Basic SCI bridge, paired request and response queues
Figure 16 – Local transaction components
Figure 17 – Local transaction components (busied by responder)
Figure 18 – Remote transaction components
Figure 19 – Remote move-transaction components
Figure 20 – Broadcast starts
Figure 21 – Broadcast resumes
Figure 22 – Transaction formats
Figure 23 – Bandwidth partitioning
Figure 24 – Resource bottlenecks
Figure 25 – Queue allocation avoids starvation
Figure 26 – Distributed cache tags
Figure 27 – Request combining
Figure 28 – Binary tree
Figure 29 – TLB purging
Figure 30 – Hardware fault-retry sequence
Figure 31 – Software fault-retry on coherent data
Figure 32 – Big-endian packet notation
Figure 33 – Big-endian register notation
Figure 34 – Send-and echo-packet formats
Figure 35 – Request-packet format
Figure 36 – Request-packet symbols
Figure 37 – Request-echo packet format
Figure 38 – Response-packet format
Figure 39 – Response-packet symbols
Figure 40 – Response-echo packet format
Figure 41 – Initialization-packet format
Figure 42 – Initialization-packet format example (companyId-based uniqueld value)
Figure 43 – Serialized implementation of 16-bit CRC
Figure 44 – Parallel CRC check
Figure 45 – Remote transaction components (local request-send damaged)
Figure 46 – Logical idle-symbol encoding
Figure 47 – Flag framing convention
Figure 48 – Logical send- and init-packet framing convention
Figure 49 – Logical echo-packet framing convention
Figure 50 – Logical sync-packet framing convention
Figure 51 – Logical packet framing convention
Figure 52 – Selected-byte reads and writes
Figure 53 – Simplified lock model
Figure 54 – Selected-byte locks (quadlet access)
Figure 55 – Selected-byte locks (octlet access)
Figure 56 – Expected DMA read transfers
Figure 57 – Expected DMA write transfers
Figure 58 – DMA block-transfer model
Figure 59 – Time-sync on SCI
Figure 60 – Elasticity model
Figure 61 – Input-synchronizer model
Figure 62 – Idle-symbol insertion
Figure 63 – Idle-symbol deletion
Figure 64 – Fair bandwidth allocation
Figure 65 – Increasing ringlet priority
Figure 66 – Restoring ringlet priority
Figure 67 – Idle-symbol creation, fair-only node
Figure 68 – Idle-symbol creation, unfair-capable node
Figure 69 – Idle consumption, fair-only node
Figure 70 – Idle consumption, unfair-capable node
Figure 71 – Pass-transmission model (fair-only node)
Figure 72 – Pass-transmission enabled
Figure 73 – Pass-transmission active
Figure 74 – Pass-transmission recovery
Figure 75 – Low/high-transmission model
Figure 76 – Low-transmission enabled
Figure 77 – Low-transmission active
Figure 78 – Low/high-transmission recovery
Figure 79 – Low/high-transmission debt repayment
Figure 80 – Low/high-transmission idle insertion
Figure 81 – High-transmission enabled
Figure 82 – Consumer send-packet queue reservations
Figure 83 – A/B age labels
Figure 84 – Response timeouts (request and no response)
Figure 85 – Time-of-death discards
Figure 86 – Packet life-cycle intervals
Figure 87 – Time-of-death generation model
Figure 88 – Responder's address-error processing
Figure 89 – Response timeouts (request and no response)
Figure 90 – Error-logging registers
Figure 91 – Scrubber maintenance functions
Figure 92 – Detecting lost low-go bits
Figure 93 – Producer's address-error processing
Figure 94 – Producer's echo-timeout processing
Figure 95 – Producer fatal-error recovery (optional)
Figure 96 – Consumer error recovery
Figure 97 – SCI (64-bit fixed) addressing
Figure 98 – Forms of node resets
Figure 99 – Receiver synchronization and scrubber selection
Figure 100 – Reset-closure generates idle symbols
Figure 101 – Idle-closure injects go-bits in idles
Figure 102 – Initialization states
Figure 103 – Initialization states (clear option)
Figure 104 – Output symbol sequence during initialization
Figure 105 – Insert-multiplexer model
Figure 106 – NodeIds after ringlet initialization and monarch selection
Figure 107 – NodeIds after emperor selection, final address assignments
Figure 108 – Flag framing convention
Figure 109 – S20 symbol encoding
Figure 110 – S20 symbol decoding
Figure 111 – S20 sync-packet encoding
Figure 112 – NODE_IDS register
Figure 113 – STATE_CLEAR fields
Figure 114 – SPLIT_TIMEOUT register-pair format
Figure 115 – ARGUMENT register-pair format
Figure 116 – CLOCK_STROBE_THROUGH format (offset 112)
Figure 117 – ERROR_COUNT register (offset 384)
Figure 118 – SYNC_INTERVAL register (offset 512)
Figure 119 – SAVE_ID register (offset 520)
Figure 120 – SLOT_ID register (offset 524)
Figure 121 – SCI ROM format (bus_info_block)
Figure 122 – ROM format, CsrOptions
Figure 123 – ROM format, LincOptions
Figure 124 – ROM format, MemoryOptions
Figure 125 – ROM format, CacheOptions
Figure 126 – DIRECTED_TARGET format
Figure 127 – Logical-to-physical address translation
Figure 128 – SCI transaction components
Figure 129 – Distributed sharing-list directory
Figure 130 – SCI coherence tags (64-byte line, 64K nodes)
Figure 131 – Prepend to ONLYP_DIRTY (pairwise capable)
Figure 132 – Memory and cache-extended components
Figure 133 – Deletion of head (and exclusive) entry
Figure 134 – Cache and memory-extended components
Figure 135 – ONLY_DIRTY list creation (minimal set)
Figure 136 – GONE list additions (minimal set)
Figure 137 – FRESH list additions (minimal set)
Figure 138 – Only-entry deletions
Figure 139 – Tail-entry deletions
Figure 140 – FRESH list creation
Figure 141 – FRESH addition to FRESH list
Figure 142 – FRESH addition to DIRTY list
Figure 143 – DIRTY addition to FRESH list
Figure 144 – DIRTY addition to DIRTY list
Figure 145 – Head purging others
Figure 146 – ONLY_FRESH list conversion
Figure 147 – HEAD_FRESH list conversion
Figure 148 – Mid-entry deletions
Figure 149 – Head-entry deletions
Figure 150 – Robust ONLY_DIRTY deletions
Figure 151 – Checked DMA reads
Figure 152 – Checked DMA write (memory FRESH)
Figure 153 – Checked DMA write (memory GONE)
Figure 154 – CLEAN list creation
Figure 155 – FRESH addition to CLEAN/DIRTY list
Figure 156 – CLEAN addition to FRESH list
Figure 157 – CLEAN addition to CLEAN/DIRTY list
Figure 158 – Washing DIRTY sharing lists (prepend conflict)
Figure 159 – Flushing a FRESH list
Figure 160 – Flushing a GONE list
Figure 161 – Cleansing DIRTY sharing lists (prepend conflict)
Figure 162 – Pairwise-sharing transitions
Figure 163 – Prepending to pairwise list
Figure 164 – Prepending to pairwise list
Figure 165 – Two stale copies, head is valid
Figure 166 – Two stale copies, tail is valid
Figure 167 – Enqolb prepending to QOLB-locked list
Figure 168 – Deqolb tail-deletion on QOLB sharing list
Figure 169 – QOLB usage
Figure 170 – Basic mread/mwrite request
Figure 171 – Memory-access response
Figure 172 – Extended coherent memory read request
Figure 173 – Cache cread and cwrite64 requests
Figure 174 – Cache cread and cwrite64 responses
Figure 175 – Linc and component signals
Figure 176 – Linc and component queues
Figure 177 – One node's transfer-cloud model
Figure 178 – The linc packet queues
Figure 179 – Node interface structure
Figure 180 – Elasticity model
Figure 181 – A memory component's packet queues
Figure 182 – An exec component's packet queues
Figure 183 – A proc component's packet queues
Figure 184 – Type 1 module and a typical subrack
Figure 185 – Module board
Figure 186 – Module injector/ejector and top and bottom shielding
Figure 187 – Front panel arrangement, module shielding and clearances
Figure 188 – Top view of subrack
Figure 189 – Front view of subrack, left end
Figure 190 – Front view of subrack, top left detail
Figure 191 – Module power and ESD connections
Figure 192 – Backplane power pinout
Figure 193 – Backplane signal pinout
Figure 194 – Slot-position backplane wiring
Figure 195 – ECL signal voltage limits
Figure 196 – Basic timing
Figure 197 – SCI power-distribution model
Figure 198 – SCI power-control signal timing
Figure 199 – Type 18-DE-500 module extender cable
Figure 200 – Arrangement of module extender cable and connector
Figure 201 – Arrangement of module extender power cable and connector
Figure 202 – Cable-link and module signal connections contrasted
Figure 203 – Pinout of outgoing cable-link connector
Figure 204 – Pinout of incoming cable-link connector
Figure 205 – Generic eye mask
Figure 206 – Line driver with transformer isolation
Figure 207 – Line driver with capacitive coupling
Figure 208 – Receiver with transformer isolation and cable equalization
Figure 209 – Receiver with capacitive isolation and cable equalization
Figure A. 1 – Simple reset
Figure A. 2 – Simple reset states
Figure B. 1 – Simple thru-counter implementation
Figure B. 2 – Direct-register TLB-purge interlock
Figure B. 3 – Coherent-TLB-purge interlock
Figure B. 4 – Enqueuing messages
Figure B. 5 – Dequeuing messages
Tables [Go to Page]
Table 1 – Packet types
Table 2 – Phase field for send packets
Table 3 – Phase field for nonbusied echoes
Table 4 – Phase field for busied echoes
Table 5 – status summary codes
Table 6 – Serial CRC-16 implementation
Table 7 – Parallel implementation of 16-bit CRC
Table 8 – Response-expected-subaction commands (read, write, and lock)
Table 9 – Responseless-subaction commands (move)
Table 10 – Event- and response-subaction commands
Table 11 – Subcommand values for Lock4 and Lock8
Table 12 – Noncoherent block-transfer hints
Table 13 – Defined SCI nodeId addresses
Table 14 – Additional SCI transaction types
Table 15 – Initial nodeId values
Table 16 – Never-implemented CSR registers
Table 17 – Physical standard description
Table 18 – Interleave-control bits
Table 19 – Memory and cache update actions
Table 20 – Stable and semistable memory-tag states
Table 21 – Stable cache-tag states
Table 22 – Stable sharing lists
Table 23 – MinimalExecute Routines
Table 24 – TypicalExecute Routines
Table 25 – Readable cache states
Table 26 – FullExecute Routines
Table 27 – Coherent transaction summary
Table 28 – Module-connector part numbers
Table 29 – Backplane-fixed-connector part numbers
Table 30 – Power-connection summary
Table 31 – Main characteristics of ECL signals for SCI
Table 32 – Cable module-like connector part number
Table 33 – Cable backplane-like connector part numbers
Table 34 – Device cable-link connector (right-angle pins)
Table 35 – Device cable-link connector (straight pins)
Table 36 – Cable cable-link connector (sockets)
Table 37 – Electrical signals at ETX
Table 38 – Electrical eye at ETX
Table 39 – Electrical signals at ERX
Table 40 – Electrical eye at ERX
Table 41 – Estimated maximum cable lengths
Table 42 – Optical eye at OTX
Table 43 – Optical eye at ORX
Table 44 – General optical requirements
Table 45 – Maximum laser spectral width
Table 46 – Typical connector properties
Table 47 – Loss budget [Go to Page]

MADCAD.com Free Trial

Report To Us

Contact us for a custom quote

⨯To continue with accurate pricing,
please select your company type below:

⨯We need your input!

⨯ We need your input!

⨯We need your input!

⨯We need your input!

Cart Warning

ISO/IEC 13961:2000 Information technology -- Scalable Coherent Interface (SCI), 2000

MADCAD.com Free Trial

Report To Us

Contact us for a custom quote

⨯To continue with accurate pricing, please select your company type below:

⨯We need your input!

⨯ We need your input!

⨯We need your input!

⨯We need your input!

Cart Warning

ISO/IEC 13961:2000 Information technology -- Scalable Coherent Interface (SCI), 2000

⨯To continue with accurate pricing,
please select your company type below: