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ISO/IEC 15776:2001 VME64bus - Specification, 2001
- CONTENTS
- FOREWORD
- INTRODUCTION
- 1 General [Go to Page]
- 1.1 Scope and object
- 1.2 Normative references
- 1.3 VMEbus interface system elements
- 1.4 VMEbus specification diagrams
- 1.5 Specification terminology
- 1.6 Protocol specification
- 1.7 System examples and explanations
- 2 Data transfer bus [Go to Page]
- 2.1 Introduction
- 2.2 Data-transfer-bus lines
- 2.3 DTB modules – Basic description
- 2.4 Typical operation
- 2.5 Data-transfer-bus acquisition
- 2.6 DTB timing rules and observations
- 3 Data transfer bus arbitration [Go to Page]
- 3.1 Bus arbitration philosophy
- 3.2 Arbitration bus lines
- 3.3 Functional modules
- 3.4 Typical operation
- 3.5 Race conditions between master requests and arbiter grants
- 4 Priority interrupt bus [Go to Page]
- 4.1 Introduction
- 4.2 Priority interrupt bus lines
- 4.3 Priority interrupt bus modules – Basic description
- 4.4 Typical operation
- 4.5 Race conditions
- 4.6 Priority interrupt bus timing rules and observations
- 5 Utility bus [Go to Page]
- 5.1 Introduction
- 5.2 Utility bus signal lines
- 5.3 Utility bus modules
- 5.4 System initialization and diagnostics
- 5.5 Power and ground pins
- 5.6 Reserved line
- 5.7 Auto slot ID
- 5.8 Auto system controller
- 6 Electrical specifications [Go to Page]
- 6.1 Introduction
- 6.2 Power distribution
- 6.3 Electrical signal characteristics
- 6.4 Bus driving and receiving requirements
- 6.5 Backplane signal line interconnections
- 6.6 User defined signals
- 6.7 Signal line drivers and terminations
- 7 Mechanical specifications [Go to Page]
- 7.1 Introduction
- 7.2 VMEbus boards
- 7.3 Front panels
- 7.4 Backplanes
- 7.5 Assembly of VMEbus subracks
- 7.6 Conduction cooled VMEbus systems
- 7.7 VMEbus backplane connectors and VMEbus board connectors
- Annexes [Go to Page]
- Annex A (normative) Glossary of VMEBus terms
- Annex B (normative) VMEBus Connector/Pin Description
- Annex C (normative) Manufacturer's Board Identification
- Rule index
- Figures [Go to Page]
- Figure 1 – System elements
- Figure 2 – Functional modules and buses
- Figure 3 – Signal timing notation
- Figure 4 – Data transfer bus functional block diagram
- Figure 5 – Block diagram – Master
- Figure 6 – Block diagram – Slave
- Figure 7 – Block diagram – Bus timer
- Figure 8 – Block diagram – Location monitor
- Figure 9 – Four ways in which 32 bits of data might be stored in memory
- Figure 10 – Four ways in which 16 bits of data might be stored in memory
- Figure 11 – Block diagram – Configuration ROM / Control & Status registers
- Figure 12 – Example of non-multiplexed address single-byte read cycle
- Figure 13 – Example of multiplexed address double-byte write cycle
- Figure 14 – Example of non-multiplexed address quad-byte write cycle
- Figure 15 – Example of eight-byte block read cycle
- Figure 16 – Data transfer bus master exchange sequence
- Figure 17 – Address broadcast timing – All cycles
- Figure 18 – A16, A24, A32 master, responding slave, and location monitor
- Figure 19 – Master, slave, and location monitor – A16, A24 and A32 address broadcast timing
- Figure 20 – Master, slave, and location monitor A16, A24, and A32 address broadcast timing
- Figure 21 – Master, slave and location monitor – A64, A40, and ADOH address broadcast timing
- Figure 22 – Master, slave and location monitor data transfer timing
- Figure 23 – Master, slave and location monitor data transfer timing
- Figure 24 – Master, slave and location monitor data transfer timing A40 multiplexed quad byte read, A40BLT multiplexed ...
- Figure 25 – Master, slave and location monitor data transfer timing
- Figure 26 – Master, slave and location monitor data transfer timing
- Figure 27 – Master, slave and location monitor data transfer timing A40 multiplexed quad byte write, A40BLT multiplexed ...
- Figure 28 – Master, slave and location monitor data transfer timing single-byte RMW cycles
- Figure 29 – Master, slave and location monitor data transfer timing double-byte RMW cycles, quad- byte RMW cycles
- Figure 30 – Address strobe inter-cycle timing
- Figure 31 – Data strobe inter-cycle timing
- Figure 32 – Data strobe inter-cycle timing
- Figure 33 – Master, slave and bus timer data transfer timing timed-out cycle
- Figure 34 – Master DTB control transfer timing
- Figure 35 – Master and slave data transfer timing master responding to RETRY* line
- Figure 36 – Master and slave data transfer timing master ignoring RETRY* line
- Figure 37 – A40, MD32 Read-Modify-Write
- Figure 38 – Rescinding DTACK timing
- Figure 39 – Arbitration functional block diagram
- Figure 40 – Illustration of the daisy chain bus grant lines
- Figure 41 – Block diagram – Arbiter
- Figure 42 – Block diagram – Requester
- Figure 43 – Arbitration flow diagram two requesters, two request levels
- Figure 44 – Arbitration sequence diagram two requesters, two request levels
- Figure 45 – Arbitration flow diagram two requesters, same request level
- Figure 46 – Arbitration sequence diagram two requesters, same request level
- Figure 47 – Priority interrupt bus functional diagram
- Figure 48 – Interrupt subsystem structure – Single handler system
- Figure 49 – Interrupt subsystem structure – Distributed system
- Figure 50 – IACKIN*/IACKOUT* DAISY-CHAIN
- Figure 51 – Block diagram – Interrupt handler
- Figure 52 – Block diagram – Interrupter
- Figure 53 – Block diagram – IACK daisy-chain driver
- Figure 54 – Release of interrupt request lines by ROAK and RORA interrupters
- Figure 55 – IACK daisy-chain driver and interrupter on the same board
- Figure 56 – Two interrupters on the same board
- Figure 57 – The three phases of an interrupt sequence
- Figure 58 – Two interrupt handlers, each monitoring one interrupt request line
- Figure 59 – Two interrupt handlers, each monitoring several interrupt request lines
- Figure 60 – Typical single handler interrupt system operation flow diagram
- Figure 61 – Typical distributed interrupt system with two interrupt handlers, flow diagram
- Figure 62 – Interrupt handler and interrupter – Interrupter selection timing single-byte, double-byte, and quad-byte ...
- Figure 63 – IACK daisy-chain driver – Interrupter selection timing single-byte, double-byte, and quad-byte interrupt ...
- Figure 64 – Participating interrupter – Interrupter selection timing single-byte, double-byte, and quad-byte interrupt ...
- Figure 65 – Responding interrupter – Interrupter selection timing single-byte, double-byte, and quad-byte interrupt ...
- Figure 66 – Interrupt handler – Status/ID transfer timing single-byte interrupt acknowledge cycle
- Figure 67 – Interrupt handler – Status/ID transfer timing double-byte and quad-byte interrupt acknowledge cycles
- Figure 68 – Responding interrupter – Status/ID transfer timing single-byte interrupt acknowledge cycle
- Figure 69 – Responding interrupter – Status/ID transfer timing double-byte interrupt acknowledge cycle quad-byte interrupt...
- Figure 70 – IACK daisy-chain driver, responding interrupter, and participating interrupter IACK daisy-chain inter-cycle ...
- Figure 71 – Utility bus block diagram
- Figure 72 – System clock driver timing
- Figure 73 – Block diagram of power monitor module
- Figure 74 – Power monitor power failure timing
- Figure 75 – Power monitor system restart timing
- Figure 76 – SYSRESET* and SYSFAIL* timing diagram
- Figure 77 – Current rating for power pins
- Figure 78 – CR/CSR auto ID slave initialization algorithm
- Figure 79 – FIRST SLOT DETECTOR (FSD)
- Figure 80 – VMEbus signal levels
- Figure 81 – Standard bus termination
- Figure 82 – Subrack with mixed board sizes
- Figure 83 – Single height board – Basic dimensions
- Figure 84 – Double height board – Basic dimensions
- Figure 85 – Connector positions on single and double height boards
- Figure 86 – Cross-sectional view of board, connector, backplane, and front panel
- Figure 87 – Optional enhanced DIN connector
- Figure 88 – Component height, lead length and board warpage
- Figure 89 – Single height, single width front panel
- Figure 90 – Double height, single width front panel
- Figure 91 – Front panel mounting brackets and dimension of single height boards
- Figure 92 – Front panel mounting brackets and dimension of double height boards
- Figure 93 – Single height filler panel
- Figure 94 – Double height filler panel
- Figure 95 – Backplane detailed dimensions of a J1 and a J2 backplane
- Figure 96 – Detailed dimensions of a J1/J2 backplane
- Figure 97 – "Off-board type" backplane terminations
- Figure 98 – "On-board type" backplane terminations
- Figure 99 – 21 Slot subrack
- Figure 100 – Board guide detail
- Tables [Go to Page]
- Table 1 – The eight categories of byte locations
- Table 2 – Address alignment on bus
- Table 3 – Signal levels during data transfers used to select which byte location(s) are accessed during a data transfer
- Table 4 – Address modifier codes
- Table 5 – Use of data lines to move data during nonmultiplexed data transfers
- Table 6 – Use of the address and data lines for multiplexed data cycles
- Table 7 – RULEs and PERMISSIONS specifying the use of the dotted lines by the various types of masters
- Table 8 – Slaves – RULEs and PERMISSIONs specifying the use of the dotted lines by the various types of slaves
- Table 9 – Use of BTO( ) mnemonic specifying the time-out period of bus timers
- Table 10 – Location monitors – RULEs and PERMISSIONs specifying the use of dotted lines by various types of location monitors
- Table 11 – Mnemonics specifying addressing capabilities
- Table 12 – Mnemonics specifying basic data transfer capabilities
- Table 13 – Mnemonics specifying block transfer capabilities
- Table 14 – The mnemonic that specifies Read-Modify-Write capabilities
- Table 15 – Transferring 32 bits of data using multiple-byte transfer cycles
- Table 16 – Transferring 16 bits of data using multiple-byte transfer cycles
- Table 17 – Mnemonic specifying unaligned transfer capability
- Table 18 – Mnemonics specifying address-only capability
- Table 19 – Configuration ROM/Control & Status registers – RULEs and PERMISSIONs or monitoring dashed lines
- Table 20 – Control and status register base definition
- Table 21 – Configuration ROM definition
- Table 22 – Timing diagrams defining master, slave, and location monitor operation
- Table 23 – Definitions of mnemonics used in tables 24, 25 and 26
- Table 24 – Use of the address and data lines to select a byte group
- Table 25 – Use of DS1*, DS0*, A1, A2, and LWORD* during the address phase of the various cycles
- Table 26 – Use of the data lines to transfer data
- Table 27 – Master, slave, and location monitor timing parameters
- Table 28 – Bus-timer timing parameters
- Table 29 – Master, timing RULEs and OBSERVATIONs
- Table 30 – Slave, timing RULEs and OBSERVATIONs
- Table 31 – Location monitor, timing OBSERVATIONs
- Table 32 – BUS TIMER, timing RULEs
- Table 33 – RULEs and PERMISSIONs specifying the use of dotted lines by the various types of arbiters
- Table 34 – RULEs and PERMISSIONs specifying the use of the dotted lines by the various types of requesters
- Table 35 – RULEs and PERMISSIONs specifying the use of the dotted lines in Figure 51 by the various types of interrupt ...
- Table 36 – RULEs and PERMISSIONs specifying the use of dotted lines in Figure 52 by the various types of interrupters
- Table 37 – Use of the IH( ) mnemonic to specify interrupt request handling capabilities
- Table 38 – Use of the I( ) mnemonic to specify interrupt request generation capabilities
- Table 39 – Mnemonics specifying Status/ID transfer capabilities
- Table 40 – Mnemonics specifying interrupt request release capabilities
- Table 41 – 3-bit interrupt acknowledge code
- Table 42 – Timing diagrams defining interrupt handler and interrupter operation
- Table 43 – Timing diagrams defining IACK daisy-chain driver operation
- Table 44 – Timing diagrams defining participating interrupter operation
- Table 45 – Timing diagrams defining responding interrupter operation
- Table 46 – Definitions of mnemonics used in Tables 47, 48 and 49
- Table 47 – Use of addressing lines during interrupt acknowledge cycles
- Table 48 – Use of the DS1*, DS0*, LWORD* and WRITE* lines during interrupt acknowledge cycles
- Table 49 – Use of the data bus lines to transfer the Status/ID
- Table 50 – Interrupt handler, interrupter and IACK DAISY-CHAIN DRIVER timing parameters
- Table 51 – Interrupt handler, timing RULEs and OBSERVATIONs
- Table 52 – Interrupter, timing RULEs and OBSERVATIONs
- Table 53 – IACK daisy-chain driver, timing RULEs and OBSERVATIONs
- Table 54 – Module drive during power-up and power-down sequences
- Table 55 – Bus voltage specification
- Table 56 – Bus driving and receiving requirements
- Table 57 – Bus driver summary
- Table 58 – J1/P1 Pin assignments
- Table 59 – J2/P2 Pin assignments [Go to Page]
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