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Content DescriptionIEC 61523-1:2023 focuses on delay and power calculation for integrated circuit design with support for modeling logical behavior and signal integrity.The standard specifications covered in this document are as follows: - Description language for timing and power modeling, called the “delay calculation language” (DCL) - Software procedural interface (PI) for communications between EDA applications and compiled libraries of DCL descriptions - Standard file exchange format for parasitic information about the chip design: Standard Parasitic Exchange Format (SPEF) - Informative usage examples - Informative notes. This is an IEC/IEEE dual logo standard. About IECThe IEC is a global, not-for-profit membership organization, whose work underpins quality infrastructure and international trade in electrical and electronic goods. The IEC facilitates technical innovation, affordable infrastructure development, efficient and sustainable energy access, smart urbanization and transportation systems, climate change mitigation, and increases the safety of people and the environment.
The IEC brings together ~170 countries and provides a global, neutral and independent standardization and conformity assessment platform for 30 000 experts globally. It administers 4 Conformity assessment systems whose members certify that devices, systems, installations, services and people work as required.
The IEC publishes around 10 000 IEC International Standards which together with conformity assessment provide the technical framework that allows governments to build national quality infrastructure and companies of all sizes to buy and sell consistently safe and reliable products in most countries of the world. IEC International Standards serve as the basis for risk and quality management and are used in testing and certification to verify that manufacturer promises are kept. |
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